The present invention relates to a data output circuit, and more specifically to a data output circuit suitable for use when driven by a single low voltage supply.
FIG. 7 is a circuit diagram showing a data output circuit related to the present invention. In FIG. 7, an output buffer circuit composed of a P-channel transistor 11 and an N-channel transistor 12 is connected to output terminals of an internal circuit 1 formed in a semiconductor chip. From the internal circuit 1, two same-phase drive signals d and d' are outputted to the gates of the P-channel transistor 11 and the N-channel transistor 12, respectively to drive the output buffer circuit. These transistors 11 and 12 are connected in series between a supply voltage (V.sub.DD) terminal and a ground voltage (V.sub.SS) terminal, and the drains of the two transistors 11 and 12 are connected in common to an output terminal D.sub.out.
When the drive signals d and d' are outputted from the internal circuit 1 to the gates of these two transistors 11 and 12, since any one of the two transistors 11 and 12 is turned on, a high-level or a low-level signal is outputted from the output terminal D.sub.out.
In this data output circuit, however, when a voltage higher than the supply voltage V.sub.DD is applied to the output terminal D.sub.out, a through current I.sub.1 flows from the output terminal D.sub.out to the supply voltage (V.sub.DD) terminal through the P-channel transistor 11.
FIG. 9 is a longitudinal cross-sectional view showing a part of the data output circuit show in FIG. 7. In FIG. 9, an n-type well 72 is formed on the surface of a p-type semiconductor substrate 71, and further a source region 73 and a drain region 74 of P.sup.+ type impurity region are formed in the n-type well 72. Here, the above-mentioned through current I.sub.1 flows from the output terminal D.sub.out into the n-type well 72 through the drain region 74.
Further, in the circuit as shown in FIG. 7, when a high-level signal is outputted, it is necessary to charge the output terminal D.sub.out through the P-channel transistor 11. In this circuit, however, since the current drive capability of the P-channel transistor is lower than that of the N-channel transistor, there exists a problem in that the data output speed is lowered.
FIG. 8 is a circuit diagram showing another data output circuit related to the present invention. In FIG. 8, the P-channel transistor 11 shown in FIG. 7 is replaced with an N-channel transistor 21. Therefore, from the internal circuit 1, two opposite-phase drive signals d and /d are outputted to the gates of the N-channel transistor 21 and the N-channel transistor 12, respectively. In the data output circuit as shown in FIG. 8, it is possible to solve the problem related to the through current I.sub.1 and the data output speed.
In the data output circuit as shown in FIG. 8, however, the maximum possible high-level output voltage is a voltage obtained by subtracting the threshold voltage of the transistor 21 from the supply voltage V.sub.DD applied to the drain of the N-channel transistor 21. Therefore, when a single low-voltage supply (e.g., the supply voltage is as low as V.sub.DD =3.3 V) is used, it is impossible to obtain a sufficient output level.
In summary, in the data output circuits as described above, when a single low voltage supply is used, there exist problems in that a through current flows or the data output speed is lowered or a sufficient output level cannot be obtained.